The Design and FPGA-Based Implementation of a Stream Cipher Based on a Secure Chaotic Generator

In this study, with an FPGA-board using VHDL, we designed a secure chaos-based stream cipher (SCbSC), and evaluated its hardware implementation performance in terms of computational complexity security. The fundamental element the system is proposed pseudo-chaotic number generator (SPCNG). architecture SPCNG includes three first-order recursive filters, each containing discrete chaotic map mixing technique internal pseudo-random (PRN). maps, namely, 3D Chebyshev (3D Ch), 1D logistic (L), skew-tent (S), are weakly coupled by predefined coupling matrix M. combined weak maps allows preserving against side-channel attacks (SCAs). was implemented on Xilinx XC7Z020 PYNQ-Z2 FPGA platform. Logic resources, throughput, cryptanalytic statistical tests showed good tradeoff between efficiency Thus, SCbSC can be used as cipher.